As integrated circuit geometries continue to plunge into the deep sub-micron regime, the issues confronted by integration technology increase in number and severity. Demands for ULSI semiconductor wiring require increasingly denser arrays with minimal spacings between narrower conductive lines. Implementation becomes problematic in manufacturing semiconductor devices having a design rule of about 0.13 micron and under.
Conventional semiconductor devices comprise a semiconductor substrate, typically doped monocrystalline silicon, and a plurality of sequentially formed interlayer dielectrics and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns on different levels, i.e., upper and lower levels, are electrically connected by a conductive plug filling a via hole, while a conductive plug filling a contact hole establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines are formed in trenches which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor “chips” comprising five or more levels of metallization are becoming more prevalent as feature sizes shrink into the deep sub-micron regime.
A conductive plug filling a via hole is typically formed by depositing an interlayer dielectric (ILD) on a patterned conductive layer comprising at least one conductive feature, forming an opening through the ILD by conventional photolithographic and etching techniques, and filling the opening with a conductive material. The excess conductive material or overburden on the surface of the ILD is typically removed by chemical-mechanical polishing (CMP). One such method is known as damascene and basically involves forming an opening in the ILD and filling the opening with a metal. Dual damascene techniques involve forming an opening comprising a lower contact or via hole section in communication with an upper trench section, which opening is filled with a conductive material, typically a metal, to simultaneously form a conductive plug in electrical contact with a conductive line.
Copper (Cu) and Cu alloys have received considerable attention as alternative metallurgy to aluminum (Al) in interconnect metallizations. Cu is relatively inexpensive, easy to process, and has a lower resistively than Al. In addition, Cu has improved electrical properties vis-à-vis tungsten (W), making Cu a desirable metal for use as a conductive plug as well as conductive wiring. However, due to Cu diffusion through dielectric materials, such as silicon dioxide, Cu interconnect structures must be encapsulated by a diffusion barrier layer. Typical diffusion barrier materials include tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium-tungsten (TiW), Tungsten (W), tungsten nitride (WN), Ti-TiN, titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), tantalum silicon nitride (TaSiN) and silicon nitride for encapsulating Cu. The use of such barrier materials to encapsulate Cu is not limited to the interface between Cu and the ILD, but includes interfaces with other metals as well.
Cu interconnect technology, by and large, has been implemented employing damascene techniques, wherein a first dielectric layer, such as a silicon oxide layer, e.g., derived from tetraethyl orthosilicate (TEOS) or silane, or a low dielectric constant material, i.e., a material having a dielectric constant of no greater than 4 (with a dielectric constant of 1 representing a vacuum), is formed over an underlying pattern having a capping layer thereon, e.g., a Cu or Cu alloy pattern with a silicon nitride capping layer. A barrier layer and optional seedlayer are then deposited, followed by Cu deposition, as by electrodeposition or electroless deposition.
In implementing conventional interconnect technology, such as damascene technology, particularly employing Cu metallization, various issues become particularly acute as the feature size continues to plunge into the deep sub-micron regime. For example, the use of a conventional metallic barrier film, such as Ta, TaN, TiN, WN and W, becomes problematic in various respects. These metallic barrier films exhibit a higher electrical resistivity than Cu, aluminum or silver. Moreover, various barrier metal films, particularly Ta and TaN, the barrier metal layers of choice, can only be deposited employing physical vapor deposition (PVD) techniques, such as sputtering. Such conventionally sputtered films exhibit poor conformal step coverage. Moreover, as feature sizes are reduced, electromigration and capacitance issues become acute along with the step coverage and resistivity problems. It also becomes more difficult to accommodate misalignment problems in multi-level interconnection technology.
Accordingly, there exists a need for improved interconnection technology, particularly for Cu damascene techniques, addressing issues generated by reduced feature sizes, such as poor step coverage, contact resistivity, electromigration, capacitance and misalignment. There exists a particular need for such improved interconnection technology for Cu damascene processing involving a highly miniaturized circuitry having a feature size less than about 0.13 micron.